What this section is for
Most of the money in a PCB order is committed before the quotation exists. Layer count, hole size, annular ring, clearance, surface finish and panelisation are all design decisions, and every one of them has a price attached that the buyer will be told about later and cannot change cheaply.
This section is about those decisions. It is written for the person who has to explain to a manager why two boards of the same size and quantity cost different amounts, and for the designer who would rather not find out at the prototype stage.
The organising idea is simple: a DFM finding costs roughly an order of magnitude more for each stage it survives. Found on the drawing, it costs an edit. Found at quotation, it costs a delay. Found at fabrication, it costs panels. Found after assembly, it costs a recall. The pages here exist to move findings to the left.
DFM is not a review of your circuit
One clarification, because it is the most common misunderstanding we deal with.
Manufacturability review asks whether a board can be built to its drawing, and whether the drawing is internally consistent. It does not ask whether the circuit works. We check whether the annular ring can survive the drill tolerance, whether the impedance target is reachable at the trace width requested, whether the panel can be routed without a sliver, whether the finish is compatible with the assembly process downstream. We do not check whether the design meets its electrical specification, and no fabricator does.
That boundary is not a limitation of effort; it is a limitation of information. A fabricator sees Gerbers and a drill file. The schematic, the timing analysis and the thermal model are not in that package, and a review that pretends otherwise would be dangerous.
The order the decisions should be made
The sequence matters because each decision constrains the next one. Made in the wrong order, decisions have to be revisited, and revisiting a stackup after routing means re-tuning every impedance-controlled net.
First: the stackup
Layer count, plane placement, dielectric thickness and copper weight. This is the page to read first, because it sets what every later rule has to fit inside. The reference stackup builds for 4, 6 and 8 layers gives four arrangements that can be handed to a fabricator, with the thickness and impedance consequences stated.
Second: impedance, if the design has it
A target of 50 Ω single-ended or 100 Ω differential is a constraint on trace width and dielectric thickness together. Once the stackup is fixed, the achievable widths are fixed, and the question becomes whether those widths fit the routing. Getting this backwards — routing first, then asking for an impedance — is the most reliable way to need a respin. The controlled impedance page covers the structures and the tolerance question.
Third: holes
Drill size, aspect ratio, annular ring and via type. Hole size is the single most direct driver of drilling cost after layer count, and the aspect ratio is what limits how small a hole can be on a thick board. An annular ring that is specified without regard to the drill tolerance is a specification that will produce breakout at some percentage of units, and the percentage is not zero.
Fourth: clearances and copper features
Minimum trace width, spacing, and the relationship between copper weight and feature size. Thicker copper etches coarser, so a design that specifies 3 oz on an outer layer and 0.1 mm traces is specifying a process that does not exist at production yield. This is the constraint that most often forces a design change late.
Fifth: surface finish
Finish is chosen by the assembly process and the storage life, not by preference. The choice interacts with pitch, with the number of assembly cycles, and with cost. It is also the decision most often made by default, which is why boards end up with a finish that is more expensive than the requirement.
Sixth: panelisation and process edges
The panel is the unit of cost. Adding two boards to a panel is worth more than most negotiation rounds and requires nobody to lose money. Tooling strips, fiducials, breakaway tabs and the direction of the weave all belong here, and all of them are decided after the design is functionally complete but before the price is fixed.
What actually moves the price
Three levers account for most of the variation between two quotations for the same board outline and quantity.
Layer count, because each lamination cycle adds imaging, pressing and drilling steps and adds yield loss. The proportional jump is largest at the first step up from single lamination, which is why four to six costs more in percentage terms than six to eight.
Panel utilisation, because the panel is bought whole. A design that tiles at 88 percent and one that tiles at 71 percent can differ by more than the margin on the order, and the difference is a drawing change rather than a negotiation.
Minimum feature size, because it sets the process, not just the difficulty. There are thresholds below which a board moves from one class of equipment to another, and the price steps at the threshold rather than sliding gradually.
Everything else — finish, thickness, colour, test method — matters, but these three are where the order of magnitude lives.
How to use this section
If you are about to release a design, read the stackup page and the file checklist. If you are arguing about a price, read the price levers and ask for a panelisation drawing. If you have a board that failed at the assembly house, start with the surface finish and the annular ring rather than with the fabricator.
The file side of the release — what a complete package contains, and which missing document causes which delay — is in the fabrication file checklist. The process that a released package goes through before it reaches a drill is described in the pre-production engineering page and, step by step, in the manufacturing process page.
What this section will cover next
The cluster continues with pages on minimum hole size and aspect ratio in practice, on annular ring and drill tolerance as a paired specification, on solder mask dams and the spacing that makes them survive, on panelisation and process edges with worked examples, and on the specific problem of warp in asymmetric builds.
Each of those will follow the same pattern as the stackup page: the decision, the constraint it creates, and what it costs when it is made late.
To have a specific design checked against these rules before it is quoted, send the Gerbers, the drill file and the layer drawing and we will return the findings with the cost consequence of each one stated.