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PCB Layer Stackup Design: Reference Builds for 4, 6 and 8 Layers
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# PCB Layer Stackup Design: Reference Builds for 4, 6 and 8 Layers
Four working stackups you can hand to a fabricator, what each one costs, and the three constraints that override any drawing: impedance target, finished thickness and copper weight.
[Discuss your requirements ↗](https://www.chinasuqi.com/en/request-a-quote/)
## The short answer
A stackup is not a layer count. It is a set of decisions about where the reference planes sit, how thick each dielectric is, and what copper weight each layer carries. The layer count is the last thing you choose, not the first.
Almost every stackup problem we see at DFM review has the same shape: the design has enough layers, but the return current has no continuous path home. Adding two layers to a board with a split ground plane does not fix it. Moving one plane does.
This page gives four builds we would accept without argument, the cost difference between them, and the three constraints that will override any drawing you make — impedance target, finished thickness, and copper weight. It is written so you can copy a build into a fabrication drawing and defend it in a design review.
One caution before the tables. A stackup is a fabrication instruction, not a suggestion. The dielectric thicknesses below are starting points that a fabricator must confirm against the actual laminate and prepreg in stock, because available glass styles change and a build that was routine in 2024 may need a substitute in 2026. The material side of that problem is covered in
[the CCL price timeline ↗](https://www.chinasuqi.com/en/blog/ccl-price-increases-2026-a-complete-timeline-of-every-notice/)
.
## What a stackup actually decides
Four things, and only one of them is about routing space.
### Impedance and the geometry that produces it
Impedance is set by trace width, dielectric thickness and dielectric constant. On a microstrip, the dielectric thickness is the distance from the trace to the plane directly beneath it, so changing the prepreg stack changes the impedance of every trace on that layer. A stackup that is 0.1 mm thinner than planned will make a 50 Ω trace into a 45 Ω trace, and no amount of tuning on the other layers recovers it.
This is why the impedance target has to exist before the stackup does. A design with a defined target and no defined stackup is a design waiting for a respin.
### Return current, which is the part people skip
Every signal trace has a return current. At DC it takes the path of least resistance. At anything above a few hundred kilohertz it takes the path of least inductance, which is directly beneath the trace on the adjacent plane. That is the whole reason planes exist.
If the plane beneath a trace is continuous, the return current flows in a narrow band under the trace and the loop area stays small. If the trace crosses a plane split, the return current has to detour around the gap, the loop area grows, and the board radiates and receives in ways that no layout rule will predict. A stackup with two ground planes and a split power plane can be perfectly fine; a stackup with one ground plane and a trace that hops across it is a problem regardless of how many layers it has.
### Thickness and warp
Finished thickness is a mechanical requirement that is usually written on a drawing as 1.6 mm without anyone checking whether the stackup can reach it symmetrically. Laminate shrinks as it cures, and a build with 0.2 mm of prepreg above the core and 0.4 mm below will bow. The bow is small at room temperature and large after reflow, which is how a board that passed incoming inspection fails at the assembly house.
### Cost, in a shape most people guess wrong
Layer count raises cost, but not proportionally. The panel is the unit of cost, and the fixed part of the panel cost — tooling, imaging setup, drilling program, test fixture — is paid whether the board has four layers or eight. What actually rises with layer count is the number of imaging, lamination and drilling steps, plus the yield loss that each additional lamination cycle introduces.
That is why the jump from four to six layers is proportionally larger than the jump from six to eight. The first jump adds a lamination cycle to a board that did not have one in the same way. The second adds steps to a process that is already a multilayer process.
## Reference build: four layers
The four-layer board is the workhorse, and it has one correct arrangement and several popular wrong ones.
The correct arrangement is signal on the outside and a plane pair inside: top signal, ground, power, bottom signal. Every signal layer has an adjacent plane, the plane pair forms a low-inductance loop for high-frequency decoupling, and the core sits in the middle where it does the most good for flatness.
The popular wrong arrangement is to run signal on all four layers and pour copper on the outer layers as a substitute for planes. A copper pour is not a reference plane. It is discontinuous wherever a trace crosses it, it is usually stitched to nothing, and it produces a board that looks like it has planes in the CAD tool and behaves like it has none.
Finished thickness for that build lands at roughly 1.6 mm, which is the most common requirement and the easiest to meet. At 1.0 mm the prepreg has to come down to about 0.1 mm and the core to about 0.7 mm, and at that point a 50 Ω microstrip on L1 needs a trace around 0.19 mm wide instead of 0.36 mm. That is still manufacturable, but it changes every width on the board and it is much easier to decide before routing than after.
Four layers reach their limit when the design needs three or more distinct power domains, or when a bus has to run across the board at an impedance that requires a plane on both sides. At that point the extra layers are not buying routing space, they are buying planes.
| Layer | Function | Typical copper | Typical dielectric to next layer |
| --- | --- | --- | --- |
| L1 | Signal, components | 1 oz (35 µm) | 0.20 mm prepreg |
| L2 | Ground plane, continuous | 1 oz | 1.06 mm core |
| L3 | Power plane, split as needed | 1 oz | 0.20 mm prepreg |
| L4 | Signal, components | 1 oz | — |
## Reference build: six layers
Six layers is where the arguments start, because six can be arranged in ways that look similar and behave very differently.
The common build puts four signal layers and two planes: signal, ground, signal, signal, power, signal. It is cheap and it is what a lot of reference designs use. Its weakness is that the two inner signal layers are adjacent with no plane between them, so they couple to each other and neither has a clean reference.
The build we recommend for anything with a clock above roughly 100 MHz uses three planes: signal, ground, signal, power, ground, signal. Now every signal layer has a plane on at least one side, the power plane is sandwiched between two grounds which is good for interplane capacitance, and the two inner grounds give the outer signal layers a return path that does not have to detour.
The trade is explicit: the three-plane build gives up one routing layer to buy a continuous return path on every signal layer. On a dense digital board that is usually the right trade. On an analog board with few nets, the four-signal build is defensible and cheaper.
A note on L4. A split power plane is normal, but a trace on L3 that crosses a split on L4 has the same return-path problem as a trace crossing a split ground. If the design needs to cross, either move the split or add a stitching capacitor across it, and document that decision. This is the single most common finding in our DFM reviews of six-layer boards.
| Layer | Function | Notes |
| --- | --- | --- |
| L1 | Signal, components | References L2 |
| L2 | Ground, continuous | Do not route on this layer |
| L3 | Signal | References L2 and L4 |
| L4 | Power, split by domain | Keep splits under areas with no L3 traces crossing |
| L5 | Ground, continuous | Second reference for L6 |
| L6 | Signal, components | References L5 |
## Reference build: eight layers
Eight layers is where a design usually has enough planes to stop compromising, and where symmetry becomes easy to achieve.
The build below is mirror-symmetric about the centre: signal and ground on the outside, a power pair in the middle, and two inner signal layers each with a ground on one side and power on the other.
This arrangement has three properties worth naming. It is symmetric in copper and in dielectric, so warp is controlled by construction rather than by luck. It gives every signal layer an adjacent plane. And the L4/L5 pair is a power-ground sandwich in the middle of the board, which is where interplane capacitance is most useful.
Eight layers also makes differential pairs easier, because a pair can be routed on an inner layer with a plane on both sides — stripline rather than microstrip. Stripline does not radiate from the trace and is not affected by what is on the surface, which is why high-speed designs move inward as they get faster. The impedance side of that decision is covered in
[the controlled impedance page ↗](https://www.chinasuqi.com/en/pcb-technologies/controlled-impedance/)
.
| Layer | Function | Notes |
| --- | --- | --- |
| L1 | Signal, components | References L2 |
| L2 | Ground, continuous | — |
| L3 | Signal, high speed | References L2 and L4 |
| L4 | Power | Pair with L5 |
| L5 | Ground | Pair with L4, second reference for L6 |
| L6 | Signal, high speed | References L5 and L7 |
| L7 | Ground, continuous | — |
| L8 | Signal, components | References L7 |
## The three constraints that override the drawing
Any stackup you draw is a proposal until these three numbers are fixed. Whichever is tightest wins, and the other two get adjusted to suit it.
### Impedance target
If the design has a 100 Ω differential pair requirement, the stackup must produce that impedance within tolerance at a trace width and spacing the fabricator can actually etch. A very thin dielectric forces very narrow traces, which raises etch tolerance as a percentage and makes the impedance harder to hold. A very thick dielectric forces wide traces, which may not fit between pads. There is a workable band in the middle, and finding it is what stackup design is.
Typical tolerance is ±10 percent, with tighter achievable when the geometry is chosen for it. Tighter than that is usually a test coupon conversation rather than a production promise, and it is worth being explicit about which one you are buying.
### Finished thickness
Thickness is set by the sum of copper and dielectric, and copper is not negligible once you go above 2 oz. A heavy-copper build that assumes 1 oz in the thickness budget will come out thick, and a fabricator who presses it to the nominal thickness will do so by thinning the dielectric, which changes the impedance. If the board needs both heavy copper and a controlled impedance, say so at quotation, because the two requirements fight.
### Copper weight
Copper weight affects etch capability: the thicker the copper, the coarser the minimum line width and spacing. A design with 0.1 mm traces and 3 oz copper is asking for a process that does not exist at reasonable yield. The rule of thumb is that each step up in copper weight costs you roughly a step in minimum feature size, and the fine-pitch devices on the outer layers are usually what sets the limit.
Where these three conflict, the usual resolution is to keep impedance and thickness as specified and to move copper weight to the inner layers, where the routing is coarser. That is a conversation to have with the fabricator before the design is released, not after.
## What layer count costs, in practice
Buyers ask for a multiplier, and the honest answer is a range, because the ratio depends on the board's other characteristics. A few structural facts are reliable enough to plan with.
The step from four to six layers is the largest proportional increase in a typical programme, because it moves the board from a single lamination to a sequential one and adds imaging and drilling passes. The step from six to eight is smaller in percentage terms for the same reason a second lamination is cheaper than the first: the process is already set up for it, and the yield learning is already paid for.
Doubling the layer count never doubles the price, and it rarely comes close. What it does do is change which cost dominates: on a four-layer board, material and process are roughly comparable; on a twelve-layer board, process and yield dominate and material is a smaller share.
If a quotation for an eight-layer board comes in at twice the four-layer price for the same area and quantity, ask what changed in the process, not what changed in the material. The answer is usually a tighter minimum line width or a smaller drill, and those are design decisions you can revisit.
There is also a 2026-specific factor on the material side. Thin glass styles used in fine-pitch, thin-dielectric builds have been the scarcest part of the laminate market, and a stackup that depends on a specific thin prepreg may face a longer lead time than the layer count suggests. If the schedule is tight, ask which glass styles the build uses and whether substitutes are approved.
## Five stackup mistakes that survive to production
These are ordered by how often we see them, not by how severe they are. All five pass DRC.
A plane with a slot in it.
A ground plane that is continuous except where a connector or a mounting hole forced a cut. The cut is invisible in the schematic and the trace that crosses it still connects, so nothing flags. The fix is to route around the slot or to bridge it, and the time to find out is before fabrication.
Two signal layers adjacent with no plane between them.
Common in six-layer boards built for routing capacity. It works at low speed and fails at high speed, and the failure looks like crosstalk that no spacing rule explains.
A stackup that is asymmetric in prepreg.
Easy to create by adjusting one dielectric to hit a thickness target. The board bows after reflow and the assembly house rejects it, and by then the panels are made.
No impedance coupon.
If the design specifies controlled impedance and the fabrication drawing does not ask for a coupon and a measurement report, you are buying a claim rather than a measurement. A coupon costs almost nothing on the panel, and the report that comes back with it is the only impedance evidence you will ever hold. What that report should contain is set out in
[the Class 2 versus Class 3 page ↗](https://www.chinasuqi.com/en/blog/ipc-a-610-class-2-vs-class-3-what-buyers-actually-pay-for/)
.
A material change approved verbally.
A substitute laminate with a different dielectric constant changes every impedance on the board. Substitution should be a written approval against the electrical requirement, not against the material family.
[The materials page ↗](https://www.chinasuqi.com/en/materials/)
covers how to specify that in a way a fabricator can actually follow.
## A worked check: 1.6 mm, eight layers, 100 Ω differential
The constraints collide in a predictable order, and walking one case is faster than reading three rules.
The requirement is a common one: eight layers, 1.6 mm finished, 100 Ω differential pairs on the outer layers and on the two inner signal layers.
Start with the thickness budget. Eight layers at 1 oz carry about 0.28 mm of copper, which leaves roughly 1.3 mm of dielectric to distribute across seven gaps and however many cores. Average that out and every dielectric would be about 0.19 mm, which sounds comfortable and is not, because the layers that need to be thin and the layers that need to be thick are not the same layers.
A 100 Ω differential pair on an outer layer is a microstrip, and microstrip has one plane and air above it, so it needs wider traces and wider spacing to reach the same impedance as a stripline carrying the same dielectric thickness. That is convenient here: the outer dielectric can be the thicker one, and the trace width stays in a range that etches comfortably.
A 100 Ω pair on an inner layer is a stripline, with a plane above and below. The same impedance is reached with narrower traces, and the dielectric that matters is the sum of the two gaps around the trace rather than a single layer. That is where the budget gets tight: if the inner gap has to be 0.1 mm to keep the total thickness at 1.6 mm, the pair becomes narrow enough that etch tolerance — which is a fixed number of microns, not a percentage — starts to eat the impedance tolerance.
The resolution is usually to stop trying to make all seven gaps equal. Put the thick dielectric on the outer layers where the microstrip wants it, keep the inner gaps at a value that leaves the stripline pair wide enough to etch reliably, and accept that the build is not uniform. Symmetry for warp is about the total copper and dielectric on each side of the centre, not about every layer being identical.
Two things follow, and both are worth writing on the drawing.
Name which layers carry impedance targets, so that nobody adjusts a dielectric to fix a thickness problem on a layer that has a 100 Ω pair on it. And ask for the coupon before the panels are made, because a coupon that measures 92 Ω is a conversation about the stackup, while a board that measures 92 Ω in the field is a conversation about returns.
## What to send us, and what we check
For a stackup review we need the layer count, the finished thickness, the impedance targets with the nets they apply to, the copper weight per layer, the material family if it is fixed, and the drill table. If the design has a heavy-copper or metal-core section, send that separately, because those builds follow different rules and mixing them into one drawing is how a quotation ends up based on assumptions nobody wrote down.
What we return is a stackup drawing with named laminate and prepreg, dielectric thickness per layer, a note on which layers carry impedance targets, and a statement of what is not achievable in the current construction and what the alternatives are. We do not silently change a dielectric to make a number work: if the build cannot reach the target, that is a question for you, not a decision for us.
A stackup review is not a circuit review. We check whether the board can be built to the drawing and whether the drawing is internally consistent. We do not check whether the design works.
If you want to see how this fits the rest of the release process,
[the DFM and design rules section ↗](https://www.chinasuqi.com/en/blog/dfm-design-rules/)
collects the pages in order, and
[the pre-production engineering page ↗](https://www.chinasuqi.com/en/resources/dfm-review/)
describes the three stages a file set goes through before it reaches a drill.
To put a specific stackup through this check,
[send the layer drawing and the impedance targets ↗](https://www.chinasuqi.com/en/request-a-quote/)
and we will return a build with the dielectrics named and the constraints stated.
Questions, answered
## Before your next build
What is the best layer stackup for a 4-layer PCB?
Signal on the outer layers, a continuous ground plane on L2 and a power plane on L3. That gives every signal layer an adjacent plane and puts the core in the middle for flatness. Pouring copper on all four layers instead of using planes is the common mistake.
Is 6 layers better than 4 for EMI?
Usually yes, but not because of the layer count. Six layers lets you put a plane on both sides of the inner routing, which gives the return current a continuous path. A four-layer board with a well-planned ground plane can be quieter than a six-layer board with a split one.
How much does an 8-layer board cost compared with 4 layers?
It is a range rather than a multiplier, and it depends on line width, drill size and quantity. Doubling the layer count does not double the price, because the panel and tooling cost is fixed. Ask for the two quotations with the same design rules and compare the process line items.
Can I change the stackup after the design is routed?
Only if the dielectric thicknesses stay the same. Changing a dielectric changes the impedance of every trace on the adjacent layer, which means re-tuning the routing. It is cheaper to fix the stackup before routing starts.
Do I need a stackup drawing if I only ask for 1.6 mm thickness?
Yes, because thickness alone does not define where the planes are. Two builds can both be 1.6 mm and behave completely differently. The drawing is what makes the requirement checkable.
CONTINUE YOUR REVIEW
## Related manufacturing resources
Explore
### [DFM and Design Rules ↗](https://www.chinasuqi.com/en/blog/dfm-design-rules/)
An index to the design decisions that set the price of a board before anyone quotes it: stackup, hole size, annular ring, clearance, surface finish and panelisation, in the order they should be decided.
technology
### [Controlled Impedance PCB Fabrication ↗](https://www.chinasuqi.com/en/pcb-technologies/controlled-impedance/)
Prepare controlled impedance PCB requirements: target values, single-ended or differential structures, reference layers, stackup and TDR verification.
guide
### [PCB materials and stackup requirements ↗](https://www.chinasuqi.com/en/materials/)
Explore FR-4, high-Tg, polyimide, high-frequency and metal-based PCB material categories and prepare a clear material specification.
technology
### [Multilayer PCB fabrication ↗](https://www.chinasuqi.com/en/pcb-technologies/multilayer/)
A multilayer board combines copper layers in a defined stackup. Confirm layer order, dielectric thickness, copper weights and materials before fabrication.
guide
### [PCB DFM & Pre-Production Engineering ↗](https://www.chinasuqi.com/en/resources/dfm-review/)
Prepare for PCB design-for-manufacturing review: consistent Gerbers, drill data, stackup, impedance and documented engineering approval.
YOUR NEXT PCB PROJECT
## Let’s define your next build.
Start with your files, requirements and target date.
[Prepare a PCB inquiry ↗](https://www.chinasuqi.com/en/request-a-quote/)

Canonical page: https://www.chinasuqi.com/en/blog/pcb-layer-stackup-design-reference-builds-for-4-6-and-8-layers/